Physical Layer Test System (PLTS) 2024

Physical Layer Test System (PLTS) 2023

Data Collection & Analysis Software for Frequency and Time Domain Data with Optional Instrument Control (Includes What’s New in PLTS 2023)

Why is Physical Layer Testing Required?

The next generation computer and communication systems now being developed will handle data rates of multiple gigabits/second. Many systems will incorporate processors and SERDES chip sets that exceed Gigahertz clock frequencies. New and troubling input/output issues are emerging as switches, routers, server blades, and storage area networking equipment moving toward 800 Gbps data rates. Digital design engineers choosing chip-to-chip, chip-to-module and backplane technologies for these systems are finding signal integrity challenges that have not been encountered before.

Traditional parallel bus topologies have run out of bandwidth. As parallel busses become wider, the complexity and cost to route on PC boards increase dramatically. The growing skew between data and clock lines has become increasingly difficult to resolve within parallel busses. The solution is fast serial channels. The newer serial bus structure has quickly replaced the parallel bus structure for high-speed digital systems. Engineers have been turning to a multitude of gigabit serial interconnect protocols with embedded clocking to achieve the goal of simple routing and more bandwidth per channel. However, these serial differential interconnects bring their own set of problems.

In order to maintain the same total bandwidth as the older parallel bus, the new serial bus needs to increase its data rate. As the data rate increases through serial interconnects, the rise time of the data transition from a zero-logic level to a one logic level becomes shorter. This shorter rise time creates larger reflections at impedance discontinuities and degrade the eye diagram at the end of the channel. As a result, physical layer components such as printed circuit board traces, connectors, cables, and IC packages can no longer be ignored. In fact, in many cases, the silicon is so fast that the physical layer device has become the bottleneck.

In order to maintain signal integrity throughout the complete channel, engineers are moving away from single ended circuits and now use differential circuits. The differential circuit provides good Common Mode Rejection Ratio (CMRR) and helps shield adjacent PCB traces from crosstalk. Properly designed differential transmission lines will minimize the undesirable effect of mode conversion and enhance the maximum data rate throughput possible. Unfortunately, differential signaling technology is not always an intuitive science.

Differential transmission lines coupled with the microwave effects of high-speed data have created the need for new design and validation tools for the digital design engineer. Understanding the fundamental properties of signal propagation through measurement and post measurement analysis is mandatory for today’s leading edge telecommunication and computer systems. The traditional Time Domain Reflectometer (TDR) is still a very useful tool, but many times the Vector Network Analyzer (VNA) is needed for the complete characterization of physical layer components. There is a strong need for a test and measurement system that will allow simple characterization of complex microwave behavior seen in high-speed digital interconnects. In fact, many digital standards groups have now recognized the importance of specifying frequency domain physical layer measurements as a compliance requirement.

Many high-speed protocols have adopted the SDD21 parameter (input differential insertion loss) as a required measurement to ensure channel compliance (Figure 3). This parameter is an indication of the frequency response that the differential signal sees as it propagates through the highspeed serial channel. An example of a proposed SDD21 compliance mask is shown in Figure 1 for the Channel Electrical Interface (CEI) working group for the Optical Internetworking Forum (OIF).