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M8062A 32 Gb/s Front-End for J-BERT M8020A High-Performance BERT

Data Sheets

M8062A 32 Gb/s

Front-End for J-BERT M8020A

High-Performance BERT

Introduction

The M8062A extends the data rate of the J-BERT M8020A Bit Error Ratio Tester to the speeds required for testing devices with lane rates in the 25-28 Gb/s range. When combined with a two channel M8041A, the system provides data pattern generation and full rate error analysis for users developing 100G class serial data link components and systems with lane rates up to 32.4 Gb/s.

Typical applications:

–Receiver characterization and compliance test

–100G Serdes (CAUI-4)

–OIF CEI 19-28 Gb/s electrical interfaces

–Backplane receivers for IEEE 802.3 100GBASE-KR4 and 25GBASE-KR

–Optical Transceiver modules and sub-components for IEEE 802.3 100GBASE-SR4, LR4, and -ER4, 32G Fibre Channel, SAS 24G

–Thunderbolt 3 (20 Gb/s)

–Active Optical Cables

Key Features

–Extends maximum data rate of J-BERT M8020A up to 32.4 Gb/s

–Jitter injection built-in and calibrated (LFPJ, HF PJ, Clk/2, BUJ, RJ, SSC)

–Integrated 8-tap de-emphasis up to 24 dB to emulate TX de-emphasis

–Built-in ISI generator for channel emulation

–Interference injection (common mode and differential mode) from single ended source

–Clean clock output with selectable dividers

–Built-in clock recovery

–Analyzer equalization eliminates errors resulting from closed eyes in loop back path

–TX Equalizer Negotiation for 100GBASE-KR4 and 25GBASE-KR

–Secure investment - options are upgradeable later

Accurate Characterization and Compliance Testing 100G Class Devices and Systems

With a data rate of up to 32.4 Gb/s, the M8062A with the J-BERT M8020A has the speed required to address 100G class serial links used in data center networking applications, as well as emerging higher speed computer bus standards such as Thunderbolt 3 and SAS 24G. In addition to supporting all of the stress types required for compliance testing to these standards, the system offers several features that greatly improve efficiency and accuracy when performing characterization tests.

Get Accurate Results Based on M8062A’s Excellent Output Performance

The eye quality of the pattern generator output is critical when characterizing many pass through devices such as TOSAs. The low intrinsic random jitter assures that you will be measuring the true performance of the device under test itself. Fast transition times preserve the eye opening at the highest data rates, maintaining margins for repeatable BER measurements.

Emulate Channel Loss with Integrated and Adjustable Inter-Symbol Interference

Most receivers designed for applications with lane rates of 25 - 28 Gb/s contain equalization to counter the effects of channel loss. The equalization design may be a multi-step continuous time linear equalizer (CTLE), or a combination of CTLE and decision feedback equalizer (DFE). Many devices include auto-optimizers which select the optimum equalization settings during a training cycle. To verify the design, the receiver must be tested with a variety of channels to create various amounts of eye closure. Because these designs have multiple CTLE gain or DFE tap settings, design verification requires inclusion of channel losses in the middle of the operating range, rather than just the minimum and maximum.

Traditionally, testing with a variety of channel losses was a tedious process, requiring changing cables between connectors on test trace boards which emulate various channel lengths. Using this method, the resolution in channel loss is limited. The potential for an auto-optimizing design to fail to converge at a particular intermediate channel loss may not be discovered during characterization testing, if the particular loss which causes the problem lies between the fixed lengths of test channels being used.

The M8062A overcomes both of these problems by offering an electronically adjustable ISI generator, for emulating channel loss. The M8062A adds electronic filters in the pattern generator data stream. The user can set one or two frequency breakpoints, and select the insertion loss value at each, providing continuously adjustable frequency dependent loss to emulate the channel.

By eliminating the need to manually move cables, characterization testing of receiver equalization becomes much more efficient.

Emulate Transmitter De-Emphasis and Compensate for Channel Loss

Virtually all transmitters 25 - 28 Gb/s lane rates include multi-tap de-emphasis. The M8062A 32 Gb/s BERT front-end offers integrated 8 tap de-emphasis, to emulate the system transmitter, or simply de-embed the cables and test fixtures from the test set-up.

Up to 8 taps can be configured as 5 post cursor, and 2 pre-cursor. Tap weights are individually settable, with essentially no interaction.

Analyze Bit Errors on Closed Eye with Integrated Analyzer Equalization

In a receiver test setup, the receiver under test is fed a test pattern from the pattern generator, and the received signal is looped back and re-transmitted to the BERT error analyzer. The loopback channel is not “stressed” to preserve the eye quality for accurate BER measurements.

At data rates above 20 Gb/s, even the clean back channel which feeds the BERT error analyzer will have some eye closure caused by the channel loss. ISI in the back channel can cause errors in the error analyzer when the eye is closed excessively, resulting in overstated bit errors.

Adding equalization capabilities to the input of the error analyzer opens partially closed eyes in the back channel, ensuring only the receiver errors from the device under test are considered in the BER measurement.

Simplify Test Set-Up With Integrated Level Interference Injection

For applications which inject interference before the channel, built-in superposition eliminates the need for external power splitters. Front-panel connectors allow superposition of external interference sources such as sine wave generators or random noise sources directly into the pattern generator data. Both common mode and differential mode injection paths are provided. The Common Mode is added at the end of the ISI channel, whereas the Differential Mode is injected before.

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